Offset interposers for large-bottom packages and large-die package-on-package structures

ABSTRACT

An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.

PRIORITY

This application is a continuation of U.S. patent application Ser. No.15/087,153, filed Mar. 31, 2016, which is a continuation of U.S. patentapplication Ser. No. 14/757,913, filed Dec. 24, 2015, which is acontinuation of U.S. patent application Ser. No. 13/977,101, filed Jun.28, 2013, all of which are incorporated by reference herein in itsentirety.

TECHNICAL FIELD

Disclosed embodiments relate to package-on-package interposers.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to understand the manner in which embodiments are obtained, amore particular description of various embodiments briefly describedabove will be rendered by reference to the appended drawings. Thesedrawings depict embodiments that are not necessarily drawn to scale andare not to be considered to be limiting in scope. Some embodiments willbe described and explained with additional specificity and detailthrough the use of the accompanying drawings in which:

FIG. 1a is a cross-section elevation of an offset interposer accordingto an example embodiment;

FIG. 1b is a cross-section elevation of an offset interposer that isdisposed on a first-level interconnect according to an exampleembodiment;

FIG. 2 is a top plan of the offset interposer depicted in FIG. 1aaccording to an example embodiment;

FIG. 3 is a cross-section elevation of an offset interposer according toan example embodiment;

FIG. 4 is a cross-section elevation of a chip package with an offsetinterposer according to an example embodiment;

FIG. 5 is a top plan cutaway of the offset interposer depicted in FIG. 4according to an example embodiment;

FIG. 6a is a cross-section elevation of a chip package with an offsetinterposer according to an example embodiment;

FIG. 6b is a cross-section elevation of a chip package with an offsetinterposer according to an example embodiment;

FIG. 7 is a cross-section elevation of a chip package with an offsetinterposer according to an example embodiment;

FIG. 8 is a cross-section elevation of a chip package with an offsetinterposer according to an example embodiment;

FIG. 9 is a process and method flow diagram according to an exampleembodiment;

and

FIG. 10 is a schematic of a computer system according to exampleembodiments.

DETAILED DESCRIPTION

Processes are disclosed where offset interposers are assembled andcoupled with microelectronic devices as chip packages. Offset interposerembodiments allow for chip-package designers to decouple interfacingchallenges such as between logic devices and memory devices during thepackaging process.

Reference will now be made to the drawings wherein like structures maybe provided with like suffix reference designations. In order to showthe structures of various embodiments more clearly, the drawingsincluded herein are diagrammatic representations of integrated circuitchips assembled to offset interposer embodiments. Thus, the actualappearance of the fabricated chip substrates, alone or in chip packages,for example in a photomicrograph, may appear different while stillincorporating the claimed structures of the illustrated embodiments.Moreover, the drawings may only show the structures useful to understandthe illustrated embodiments. Additional structures known in the art maynot have been included to maintain the clarity of the drawings.

FIG. 1a is a cross-section elevation of an offset interposer 100according to an example embodiment. The offset interposer 100 includes acenter through hole 108 (also referred to as an inner edge 108) which isprovided to allow clearance for a first-level device such as aprocessor. Similarly, an interposer lateral edge 106 (also referred toas an outer edge 106) defines the outer lateral surface and perimeter ofthe offset interposer 100.

The offset interposer 100 also includes a land side 112 that isconfigured to interface with a first-level interconnect such as apackage for a processor. Opposite the land side 112 is apackage-on-package (POP) side 110 onto which a POP structure such as amemory module is to be assembled.

Two adjacent, spaced-apart land-side pads 114 and 116 (indicated withtwo occurrences for each side in cross section) are disposed on the landside 112. The land-side pads 114 and 116 are part of a land-sideball-grid array (BGA) that is configured to interface with a first-levelinterconnect. Similarly, two adjacent spaced-apart POP-side pads 118 and120 (indicated with two occurrences for each side in cross section) aredisposed on the POP side 110. It can be seen that for the two land-sidepads 114 and 116, they have a different X-Y orientation than the twoPOP-side pads 118 and 120 (where the Y-direction is orthogonal to theplane of the FIG). This means the POP-side pads 118 and 120, althoughthey are coupled through the interposer to the respective land-side pads114 and 116, they are offset or “translated” in at least one of the X-or Y-direction; in these illustrated embodiments, in the X-direction.

A given POP-side pad 118 is coupled to a given land-side pad 114 througha first trace 124 and useful vias 125. Similarly, a given adjacent andspaced-apart POP-side pad 120 is coupled to a corresponding givenland-side pad 116 through a second trace 126 and useful vias 127.

As indicated on the offset interposer 100 at the right side thereof, aland-side pad spacing 128 and a POP-side pad spacing 130 define the padcenter-to-center spacings of the respective sides. In an embodiment, theland-side-pad spacing 128 is configured to match conventional padspacings that interface conventional first-level ball-grid array (BGA)interconnects. In an embodiment, the POP-side pad spacing 130 is equalto the land-side pad spacing 128. In an embodiment, the POP-side padspacing 130 is 0.5 mm. In an embodiment, the land-side pad spacing 128is 0.5 mm. In an embodiment, the POP-side pad spacing 130 is 0.5 mm andthe land-side pad spacing 128 is less than 0.5 mm. In an embodiment, thePOP-side pad spacing 130 is unity and the land-side pad spacing 128 isless than unity such as 80% of unity. In an embodiment, the POP-side padspacing 130 is 0.5 mm and the land-side pad spacing 128 is 0.4 mm.

The POP-side pads 118 and 120 are offset or translated in theX-direction with respect to the land-side pads 114 and 116,respectively. As illustrated, the land-side pads 114 and 116 have aland-side perimeter characteristic dimension 134 and the POP-side pads118 and 120 have a POP-side perimeter characteristic dimension 132. Itis seen in this embodiment, that the land-side perimeter characteristicdimension 134 is larger than the POP-side perimeter characteristicdimension 134. When observed in plan view (see FIG. 2), the POP-sidepads are arrayed with a perimeter that is less than but concentric withthe perimeter of the land-side pads.

In an embodiment, offset of the POP-side pads 118 and 120 is such thatthe POP-side perimeter characteristic dimension 132 is less than that ofthe land-side perimeter characteristic dimension 134 such that theX-length of the traces 124 and 126 is less than that depicted in FIG. 1a. In an embodiment, offset of the POP-side pads 118 and 120 is such thatthe POP-side perimeter characteristic dimension 132 is less than that ofthe land-side perimeter characteristic dimension 134 such that thetraces 124 and 126 depicted in FIG. 1a are not needed. For example,where the trace 124 is not needed, the footprint of the POP-side pad 118overlaps the footprint of the land-side pad 114. The via 125interconnects the two respective pads 118 and 114 by direct contactthrough the interposer 100 (see FIG. 3). In other words, the POP-sidepad 118 has a different footprint that its corresponding land-side pad114. Similarly for example, where the trace 126 is not needed, thefootprint of the POP-side pad 120 overlaps the footprint of theland-side pad 116 and the via 127 interconnects the two respective pads120 and 116 by direct contact through the interposer 100.

FIG. 2 is a top plan of the offset interposer 100 depicted in FIG. 1aaccording to an example embodiment. Two occurrences each of thespaced-apart but adjacent land-side pads 114 and 116 are indicated withphantom lines as they are below the POP side 110 in a POP-side land-gridarray (LGA). Similarly, two occurrences each of two spaced-apart butadjacent POP-side pads 118 and 120 are indicated disposed on the POPside 110 in a land-side BGA.

As seen at the cross-section line 1 a, the POP-side pads 118 and 120 areoffset in the X-direction with respect to the land-side pads 114 and116, respectively. As illustrated, the land-side pads 114 and 116 havethe land-side perimeter characteristic dimension 134 and the POP-sidepads 118 and 120 have the POP-side perimeter characteristic dimension132. It is seen in this embodiment, that the land-side perimetercharacteristic dimension 134 is larger than the POP-side perimetercharacteristic dimension 134. It is also seen that no footprint overlapof the POP-side pads 118 and 120 occurs with the land-side pads 114 and116. In an embodiment however, some footprint overlap of the POP-sidepads 118 and 120 occurs with the land-side pads 114 and 116. (See FIG.3).

Because there may be a one-to-one correspondence between POP-side padsthat are coupled to land-side pads, several dummy land-side pads may bepresent that may be used, however, for increased thermal and physicalshock bolstering as well as for extra power and/or ground current flow.As an illustrated embodiment, 56 POP-side pads are depicted on the POPside 110, but where center-to-center pitch and pad size are matchedbetween the POP side 110 and the land side 112, as many as 88 land-sidepads are located on the land side 112.

FIG. 1b is a cross-section elevation of a chip package 101 with anoffset interposer 100 according to an example embodiment. The offsetinterposer 100 illustrated in FIG. 1a is depicted mounted upon afirst-level interconnect 136 such as a mounting substrate for anelectronic device 138. The first-level interconnect 136 may be referredto as a large-bottom package since the POP-side perimeter characteristicdimension 132 is smaller than the land-side characteristic dimension134.

In an embodiment, the electronic device 138 is a processor such as onemanufactured by Intel Corporation of Santa Clara, Calif. In anembodiment, the processor is an Atom® processor. In an embodiment, theprocessor is the type from Intel Corporation that is code-namedPenwell™. The electronic device 138 is mounted flip-chip fashion uponthe first-level interconnect 136 and it has an active surface 140 and abackside surface 142. Other configurations of a chip upon thefirst-level interconnect 136 may include a wire-bond chip with theactive surface facing away from the first-level interconnect 136. Thefirst-level interconnect 136 is also configured to communicate to afoundation substrate 144 such as a smartphone motherboard, though anelectrical array such as a ball-grid array that is illustrated withseveral electrical bumps 146. Other ways to connect the first-levelinterconnect include a land-grid array in the place of electrical bumps.

The offset interposer 100 is coupled to the first-level interconnect 136by a series of electrical bumps 115 and 117 that correspond to theland-side pads 114 and 116 depicted in FIGS. 1a and 2. The electricalbumps 115 and 117 are disposed on the land-side 112. Similarly, a seriesof electrical bumps 119 and 121 are disposed on the POP-side 110. Theseries of electrical bumps 119 and 121 correspond to the POP-side pads118 and 120, respectively, depicted in FIGS. 1a and 2. The series ofelectrical bumps 119 and 121 are POP-side interconnects. The electricalbumps 119 and 121 are depicted for illustrative purposes as they wouldlikely be part of a POP package such that the POP-side pads 118 and 120are part of a POP LGA.

Because of the translated effect of the offset interposer 100, a usefulkeep-out zone (KOZ) 150 for underfill material 152 may be maintained,and a larger logic die 138, has a useful underfill amount while theseries of bumps 115 and 117 remains protected from contamination by theunderfill material 152.

In an embodiment, the chip package 101 is assembled to a computingsystem that has a smartphone form factor. In an embodiment, the chippackage 101 is assembled to a computing system that has a tablet formfactor.

FIG. 3 is a cross-section elevation of an offset interposer 300according to an example embodiment. The offset interposer 300 includes acenter through hole 308 which is provided to allow clearance for afirst-level device such as a processor. Similarly, an interposer lateraledge 306 defines the outer lateral surface of the offset interposer 300.The offset interposer 300 also includes a land side 312 that isconfigured to interface with a first-level interconnect such as apackage for a processor. Opposite the land side 312 is a POP side 310.

Two adjacent, spaced-apart land-side pads 314 and 316 are disposed onthe land side 312. Similarly, two adjacent spaced-apart POP-side pads318 and 320 are disposed on the POP side 310. A given POP-side pad 318is coupled to a given land-side pad 314 through a useful vias 325.Similarly, a given adjacent and spaced-apart POP-side pad 320 is coupledto a corresponding given land-side pad 316 through useful vias 327.

As indicated on the offset interposer 300 at the right side thereof, aland-side pad spacing 328 and a POP-side pad spacing 330 define thecenter-to-center pad spacings of the respective sides. In an embodiment,the land-side-pad spacing 328 is configured to match conventional padspacings that interface conventional first-level interconnects. In anembodiment, the POP-side pad spacing 330 is equal to the land-side padspacing 328. In an embodiment, the POP-side pad spacing 330 is 0.5 mm.In an embodiment, the land-side pad spacing 328 is 0.5 mm. In anembodiment, the POP-side pad spacing 330 is 0.5 mm and the land-side padspacing 328 is less than 0.5 mm. In an embodiment, the POP-side padspacing 330 is unity and the land-side pad spacing 328 is less thanunity such as 80% of unity. In an embodiment, the POP-side pad spacing330 is 0.5 mm and the land-side pad spacing 328 is 0.4 mm.

The POP-side pads 318 and 320 are offset or translated in theX-direction with respect to the land-side pads 314 and 316,respectively. As illustrated, the land-side pads 314 and 316 have aland-side perimeter characteristic dimension 334 and the POP-side pads318 and 320 have a POP-side perimeter characteristic dimension 332. Itis seen in this embodiment, that the land-side perimeter characteristicdimension 334 is larger than the POP-side perimeter characteristicdimension 334. When observed in plan view, the POP-side pads are arrayedwith a perimeter that is less than but concentric with the perimeter ofthe land-side pads.

As illustrated according to an embodiment, offset of the POP-side pads318 and 320 is such that the POP-side perimeter characteristic dimension332 is less than that of the land-side perimeter characteristicdimension 334 such that the traces 124 and 126 depicted in FIG. 1a arenot needed. For example, the footprint of the POP-side pad 318 overlaps(in the X-direction when projected in the Z-direction) the footprint ofthe land-side pad 314 and the via 325 interconnects the two respectivepads 318 and 314 by direct contact. Similarly for example, the footprintof the POP-side pad 320 overlaps the footprint of the land-side pad 316and the via 327 interconnects the two respective pads 320 and 318 bydirect contact. In an embodiment, overlap of the POP-side pad by theland-side pad is 100 percent. In an embodiment, overlap of the POP-sidepad by the land-side pad is in a range from 1 percent to less than 100percent. In an embodiment, overlap of the POP-side pad by the land-sidepad is less than 50 percent. This embodiment is illustrated in FIG. 3.In an embodiment, overlap of the POP-side pad by the land-side pad isgreater than 50 percent. It may now be appreciated that one embodimentincludes the X-Y footprint of the POP-side pads 114 and 116 is exclusiveof the X-Y footprint projection of the two corresponding land-side pads118 and 120. This means there is no overlap of the X-Y footprint of anyPOP-side pad with its land-side pad projection. This embodiment may beseen illustrated in FIG. 1a . and FIG. 2.

It may now be appreciated that the perimeter that is defined by thePOP-side perimeter characteristic dimension 132 is closer to the inneredge 108 than the perimeter that is defined by the land-side perimetercharacteristic dimension 134. As illustrated, the land-side perimetercharacteristic dimension 134 is closer to the outer edge 106 than thePOP-side perimeter characteristic dimension 132. In an embodiment, thetwo characteristic dimensions 132 and 134 are the same. In all otherembodiments, the land-side perimeter characteristic dimension 134 iscloser to the outer edge 106 and the POP-side perimeter characteristicdimension 132 is closer to the inner edge 108.

FIG. 4 is a cross-section elevation of a chip package 401 with an offsetinterposer 400 according to an example embodiment. In an embodiment, thechip package 401 is assembled to a computing system that has a tabletform factor. In an embodiment, the chip package 401 is assembled to acomputing system that has a smartphone form factor.

The offset interposer 400 illustrated in FIG. 4 is depicted mounted upona first-level interconnect 436 such as a mounting substrate for anelectronic device 438. The electronic device 438 is mounted flip-chipfashion upon the first-level interconnect 436 and it has an activesurface 440 and a backside surface 442. Other configurations of a chipupon the first-level interconnect 436 may include a wire-bond chip withthe active surface facing away from the first-level interconnect 436.The first-level interconnect 436 is also configured to communicate to afoundation substrate such as the foundation substrate 144 depicted inFIG. 1a . The foundation substrate may be a tablet motherboard that iscommunicated to by an electrical array such as a ball-grid array that isillustrated with several electrical bumps 446.

The offset interposer 400 is coupled to the first-level interconnect 436by a series of electrical bumps 415 and 417 that correspond to land-sidepads on the land-side surface 410. The electrical bumps 415 and 417 aredisposed on the land-side 412. Similarly, a series of electrical bumps419, 421, and 453 are disposed on the POP-side 410. The electrical bumps419, 421, and 453 are depicted for illustrative purposes as they wouldlikely be part of a POP package such that the POP-side pads (such as thePOP-side pads 118 and 120, depicted in FIG. 1a ) are part of a POP LGA.

At the left side of the cross section, three electrical bumps 419, 421,and 453 are seen, but on the right side thereof, only two electricalbumps 419 and 421 are seen in this cross section according to anembodiment. Further to the illustrated embodiment, POP-side pad spacing430 is greater than land-side pad spacing 428. The bump count may be thesame on both the land-side 412 and the POP-side 410, however, by virtueof the smaller land-side spacing 428, which allows a denser bump arrayon the land-side 412 than that on the POP-side 410. In an exampleembodiment, the bump count is the same on the POP side 410 as on theland-side 412. In an example embodiment, the bump count on the land-side412 is 88 and it is the same on the POP side 410 as on the land-side412.

In an embodiment, the POP-side bumps 419, 421, and 453 accommodate a POPpackage (not pictured, see, e.g., FIGS. 6, 7, and 8) that has the sameX-Y dimensions as the offset interposer 400. The difference, however, isthe electrically connected POP-side bumps 419, 421, and 453 on the POPside 410 are set at a larger pitch than the electrically connectedland-side bumps 415 and 417.

As indicated on the offset interposer 400 at the left side thereof, aland-side pad spacing 428 and a POP-side pad spacing 430 define the padspacings of the respective sides. In an embodiment, the POP-side padspacing 430 is 0.5 mm and the land-side pad spacing 428 is 0.4 mm. Othercomparative POP- to land-side pad spacing embodiments set forth in thisdisclosure may be applied to the illustration.

In an embodiment, the land-side-pad spacing 428 is configured to matchconventional pad spacings that interface conventional first-levelinterconnects. In an embodiment, the POP-side pad spacing 430 is equalto the land-side pad spacing 428. In an embodiment, the POP-side padspacing 430 is 0.5 mm. In an embodiment, the land-side pad spacing 428is 0.5 mm. In an embodiment, the POP-side pad spacing 430 is 0.5 mm andthe land-side pad spacing 428 is less than 0.5 mm. In an embodiment, thePOP-side pad spacing 430 is unity and the land-side pad spacing 428 isless than unity such as 80% of unity.

It may now be appreciated that the offset interposer 400 may haveland-side pads that accommodate a two-bump row of electricalconnections, but the POP-side pads accommodate a three-bump row ofelectrical connections. In an example embodiment, a memory module thatis to be mounted onto the POP bumps 419, 421, and 453 is accommodatedand adapted to a larger logic die 438 by using a tighter-pitch array ofland-side bumps 415 and 417 that is configured as a two-bump row ofelectrical connections. In an embodiment, the chip package 401 isassembled to a computing system that has a tablet form factor.

FIG. 5 is a top plan cutaway 500 of the offset interposer 400 depictedin FIG. 4 according to an example embodiment. The offset interposer 400depicted in FIG. 4 is illustrated at the section line 4. It can be seenwhen sighting from left-to-right along the X-direction that the seriesof electrical bumps 419, 421, and 453 on the left side is intermingledas a row of three bumps positioned between alternating rows of twobumps. Similarly on the right side, a series of electrical bumps 419 and421 is intermingled as a row of two bumps positioned between alternatingrows of three bumps according to an embodiment. In an embodiment, thetwo-bump row, three-bump row configuration may be mixed and matched. Itis seen that in the bottom right, two three-bump rows are spaced apartand adjacent to each other.

As illustrated, the series of electrical bumps 419, 421, 453 (andcontinuing from left-to-right) 421 and 419 help to define the POP-sideperimeter characteristic dimension 432.

FIG. 6a is a cross-section elevation of a chip package 601 with anoffset interposer 600 according to an example embodiment. The offsetinterposer 600 illustrated in FIG. 6 is depicted mounted upon afirst-level interconnect 636 such as a mounting substrate for anelectronic device 638. The first-level interconnect 636 is also depictedmounted upon a foundation substrate 644 according to any of theembodiments set forth in this disclosure. The electronic device 638 ismounted flip-chip fashion upon the first-level interconnect 636.

A POP substrate 654 is mounted on electrical bumps that are on the POPside of the offset interposer 600. The POP substrate 654 is depictedwith a POP device 658 such as a memory die 656.

It may now be appreciated that the offset interposer 600 may haveland-side pads that accommodate, e.g., a 12×12 mm landing onto thefirst-level interconnect 636 and the POP-side pads accommodate a POPsubstrate 654 that is smaller than the 12×12 size example. Thus, wherethe footprint of the offset interposer 600 onto the first-levelinterconnect 636 is, e.g., 12×12 mm, and where the POP device 656 issmaller, the offset interposer 600 accommodates the smaller size of thePOP device 656 without disrupting what may be a useful 12×12 mm size ofthe footprint of the interposer 600 upon the first-level interconnect636.

It may now be appreciated that the offset interposer 600 may haveland-side pads that accommodate, e.g., a 14×14 mm landing that is neededfor a given electronic device 638, while the landing size onto thefirst-level interconnect 636 is needed to be 14×14 mm, the POP-side padsaccommodate a POP substrate 654 that is smaller but perhaps a useful,e.g., 12×12 mm footprint. In an example embodiment, a larger processor638 is needed but a POP substrate 654 has a 12×12 mm footprint onto theoffset interposer 600. It may now be appreciated that all comparativepad spacing embodiments may be applied to the illustration.

FIG. 6b is a cross-section elevation of a chip package 603 with anoffset interposer 400 according to an example embodiment. The offsetinterposer 400 illustrated in FIG. 6 is depicted mounted upon afirst-level interconnect 636 such as a mounting substrate for anelectronic device 638. The first-level interconnect 636 is also depictedmounted upon a foundation substrate 644 according to any of theembodiments set forth in this disclosure. The electronic device 638 ismounted flip-chip fashion upon the first-level interconnect 636.

A POP substrate 654 is mounted on electrical bumps that are on the POPside of the offset interposer 600. The POP substrate 654 is depictedwith a POP device 658 such as a memory die 656.

It may now be appreciated that the offset interposer 400 and the POPsubstrate 654 may have similar X-Y form factors. It may now beappreciated that all comparative pad spacing embodiments may be appliedto the illustration.

FIG. 7 is a cross-section elevation of a chip package 701 with an offsetinterposer 700 according to an example embodiment. The offset interposer700 illustrated in FIG. 7 is depicted mounted upon a first-levelinterconnect 736 such as a mounting substrate for an electronic device738. The first-level interconnect 736 is also depicted mounted upon afoundation substrate 744 according to any of the embodiments set forthin this disclosure. The electronic device 738 is mounted flip-chipfashion upon the first-level interconnect 736. A stacked die 758 ismounted on the electronic device 738 according to an embodiment. Thestacked die 754 is a wire-bonded device that is in electricalcommunication with other devices through the first-level interconnect736 depicted in the chip package 701.

A POP substrate 754 is mounted on electrical bumps that are on the POPside of the offset interposer 700. The POP substrate 754 is depictedwith a POP device such as a memory die 756. In an embodiment, thestacked device 758 is a radio frequency (RF) die and the POP device 756is a memory die.

It may now be appreciated that the offset interposer 700 may haveland-side pads that accommodate, e.g., a 12×12 mm landing onto thefirst-level interconnect 736 and the POP-side pads accommodate a POPsubstrate 754 that is smaller than the 12×12 size example, butsufficient clearance is provided between the first-level interconnect636 and the POP substrate 754 to accommodate both the electronic device738 and the stacked die 758. Thus, where the footprint of the offsetinterposer 700 onto the first-level interconnect 736 is, e.g., 12×12 mm,and where the POP device 756 is smaller, the offset interposer 700accommodates the smaller size of the POP device 756 without disruptingwhat may be a useful size of the footprint of the interposer 700 uponthe first-level interconnect 736.

It may now be appreciated that the offset interposer 700 may haveland-side pads that accommodate, e.g., a 14×14 mm landing that is neededfor a given electronic device 738, while the landing size onto thefirst-level interconnect 736 is needed to be 14×14 mm, the POP-side padsaccommodate a POP substrate 754 that is smaller but perhaps a useful12×12 mm footprint. In an example embodiment, a larger processor 738 isneeded but a POP substrate 754 has a 12×12 mm footprint onto the offsetinterposer 700. It may now be appreciated that all comparative padspacing embodiments may be applied to the illustration.

It may now be appreciated that an offset interposer such as the offsetinterposer 400 depicted in FIG. 4 may be used in FIG. 7 in the place ofthe offset interposer 700, where a three-ball-count row configuration istranslated from the POP side to a two-ball-count row configuration onthe land-side.

FIG. 8 is a cross-section elevation of a chip package 801 with an offsetinterposer 800 according to an example embodiment. The offset interposer800 illustrated in FIG. 8 is depicted mounted upon a first-levelinterconnect 836 such as a mounting substrate for an electronic device838. The first-level interconnect 836 is also depicted mounted upon afoundation substrate 844 according to any of the embodiments set forthin this disclosure. The electronic device 838 is mounted flip-chipfashion upon the first-level interconnect 836. The electronic device 838is depicted as a through-silicon (through the die) via (TSV) 839 device838 and a stacked die 858 is mounted flip-chip fashion on the TSVelectronic device 838 according to an embodiment. The stacked die 854 isa flip-chip device that is in electrical communication with otherdevices through the first-level interconnect 836 by the TSVs 839depicted in the chip package 801.

A POP substrate 854 is mounted on electrical bumps that are on the POPside of the offset interposer 800. The POP substrate 854 is depictedwith a POP device such as a memory die 756. In an embodiment, thestacked device 858 is a memory die and the POP device 856 is wire-bondedRF device 856.

It may now be appreciated that the offset interposer 800 may haveland-side pads that accommodate, e.g., a 12×12 mm landing onto thefirst-level interconnect 836 and the POP-side pads accommodate a POPsubstrate 854 that is smaller than the 12×12 size example, butsufficient clearance is provided between the first-level interconnect836 and the POP substrate 854 to accommodate both the TSV electronicdevice 838 and the stacked die 858. Thus, where the footprint of theoffset interposer 800 onto the first-level interconnect 836 is, e.g.,12×12 mm, and where the POP device 856 is smaller, the offset interposer800 accommodates the smaller size of the POP device 856 withoutdisrupting what may be a useful size of the footprint of the interposer800 upon the first-level interconnect 836.

It may now be appreciated that the offset interposer 800 may haveland-side pads that accommodate, e.g., a 14×14 mm landing that is neededfor a given TSV electronic device 838, while the landing size onto thefirst-level interconnect 836 is needed to be 14×14 mm, the POP-side padsaccommodate a POP substrate 854 that is smaller but perhaps a useful12×12 mm footprint. In an example embodiment, a larger TSV processor 838is needed but a POP substrate 854 has a 12×12 mm footprint onto theoffset interposer 800. It may now be appreciated that all comparativepad spacing embodiments may be applied to the illustration.

It may now be appreciated that an offset interposer such as the offsetinterposer 400 depicted in FIG. 4 may be used in FIG. 8 in the place ofthe offset interposer 800, where a three-ball-count row configuration istranslated from the POP side to a two-ball-count row configuration onthe land-side.

FIG. 9 is a process and method flow diagram according to exampleembodiments.

At 910, a process embodiment includes forming an offset interposer. Anoffset interposer may be built by known technique to achieve the severaldisclosed embodiment. For example, formation of an offset interposerincludes laminating traces and BGA pads onto a core with a usefulconfiguration of translated pads when comparing POP side pad placementto land-side pad placement.

At 912, an embodiment of building the offset interposer includes makingthe ball-pad pitch on the POP side the same as that on the land side. Itmay now be understood that ball-pad pitch may be different on one sidecompared to the other side.

At 914, an embodiment of building the offset interposer includes makingthe POP-side pads overlap the landside pads. In an non-limiting exampleembodiment, the POP-side pads 318 and 320 overlap their correspondingland-side pads 314 and 316, respectively.

At 915, an embodiment of building the offset interposer includescoupling the POP-side pad with its corresponding land-side pad by directcontact only with a via.

At 920, a method of assembling an offset interposer to a first-levelinterconnect includes mating the land-side of pads to electrical bumpsthat are disposed on a first-level interconnect.

At 930, a method embodiment includes assembling the offset interposer toa POP substrate.

At 940, a method embodiment includes assembling the offset interposer toa computing system.

FIG. 10 is a schematic of a computer system according to an embodiment.The computer system 1000 (also referred to as the electronic system1000) as depicted can embody an offset interposer according to any ofthe several disclosed embodiments and their equivalents as set forth inthis disclosure. An apparatus that includes an offset interposer that isassembled to a computer system. The computer system 1000 may be asmartphone. The computer system 1000 may be a tablet computer. Thecomputer system 1000 may be a mobile device such as a netbook computer.The computer system 1000 may be a desktop computer. The computer system1000 may be integral to an automobile. The computer system 1000 may beintegral to a television. The computer system 1000 may be integral to aDVD player. The computer system 1000 may be integral to a digitalcamcorder.

In an embodiment, the electronic system 1000 is a computer system thatincludes a system bus 1020 to electrically couple the various componentsof the electronic system 1000. The system bus 1020 is a single bus orany combination of busses according to various embodiments. Theelectronic system 1000 includes a voltage source 1030 that providespower to an integrated circuit 1010. In some embodiments, the voltagesource 1030 supplies current to the integrated circuit 1010 through thesystem bus 1020.

The integrated circuit 1010 is electrically coupled to the system bus1020 and includes any circuit, or combination of circuits according toan embodiment. In an embodiment, the integrated circuit 1010 includes aprocessor 1012 that can be of any type of an apparatus that includes anoffset interposer embodiment. As used herein, the processor 1012 maymean any type of circuit such as, but not limited to, a microprocessor,a microcontroller, a graphics processor, a digital signal processor, oranother processor. In an embodiment, SRAM embodiments are found inmemory caches of the processor 1012. Other types of circuits that can beincluded in the integrated circuit 1010 are a custom circuit or anapplication-specific integrated circuit (ASIC), such as a communicationscircuit 1014 for use in non-equivalent wireless devices such as cellulartelephones, smartphones, pagers, portable computers, two-way radios, andother electronic systems. In an embodiment, the processor 1010 includeson-die memory 1016 such as static random-access memory (SRAM). In anembodiment, the processor 1010 includes embedded on-die memory 1016 suchas embedded dynamic random-access memory (eDRAM).

In an embodiment, the integrated circuit 1010 is complemented with asubsequent integrated circuit 1011 such as a graphics processor or aradio-frequency integrated circuit or both as set forth in thisdisclosure. In an embodiment, the dual integrated circuit 1010 includesembedded on-die memory 1017 such as eDRAM. The dual integrated circuit1011 includes an RFIC dual processor 1013 and a dual communicationscircuit 1015 and dual on-die memory 1017 such as SRAM. In an embodiment,the dual communications circuit 1015 is particularly configured for RFprocessing.

In an embodiment, at least one passive device 1080 is coupled to thesubsequent integrated circuit 1011 such that the integrated circuit 1011and the at least one passive device are part of the any apparatusembodiment that includes an offset interposer that includes theintegrated circuit 1010 and the integrated circuit 1011. In anembodiment, the at least one passive device is a sensor such as anaccelerometer for a tablet or smartphone.

In an embodiment, the electronic system 1000 includes an antenna element1082 such as any coreless pin-grid array substrate embodiment set forthin this disclosure. By use of the antenna element 1082, a remote device1084 such as a television, may be operated remotely through a wirelesslink by an apparatus embodiment. For example, an application on a smarttelephone that operates through a wireless link broadcasts instructionsto a television up to about 30 meters distant such as by Bluetooth®technology. In an embodiment, the remote device(s) includes a globalpositioning system of satellites for which the antenna element(s) areconfigured as receivers.

In an embodiment, the electronic system 1000 also includes an externalmemory 1040 that in turn may include one or more memory elementssuitable to the particular application, such as a main memory 1042 inthe form of RAM, one or more hard drives 1044, and/or one or more drivesthat handle removable media 1046, such as diskettes, compact disks(CDs), digital variable disks (DVDs), flash memory drives, and otherremovable media known in the art. In an embodiment, the external memory1040 is part of a POP package that is stacked upon an offset interposeraccording to any disclosed embodiments. In an embodiment, the externalmemory 1040 is embedded memory 1048 such an apparatus that includes anoffset interposer mated to both a first-level interconnect and to a POPmemory module substrate according to any disclosed embodiment.

In an embodiment, the electronic system 1000 also includes a displaydevice 1050, and an audio output 1060. In an embodiment, the electronicsystem 1000 includes an input device such as a controller 1070 that maybe a keyboard, mouse, touch pad, keypad, trackball, game controller,microphone, voice-recognition device, or any other input device thatinputs information into the electronic system 1000. In an embodiment, aninput device 1070 includes a camera. In an embodiment, an input device1070 includes a digital sound recorder. In an embodiment, an inputdevice 1070 includes a camera and a digital sound recorder.

A foundation substrate 1090 may be part of the computing system 1000. Inan embodiment, the foundation substrate 1090 is a motherboard thatsupports an apparatus that includes an offset interposer. In anembodiment, the foundation substrate 1090 is a board which supports anapparatus that includes an offset interposer. In an embodiment, thefoundation substrate 1090 incorporates at least one of thefunctionalities encompassed within the dashed line 1090 and is asubstrate such as the user shell of a wireless communicator.

As shown herein, the integrated circuit 1010 can be implemented in anumber of different embodiments, an apparatus that includes an offsetinterposer according to any of the several disclosed embodiments andtheir equivalents, an electronic system, a computer system, one or moremethods of fabricating an integrated circuit, and one or more methods offabricating and assembling an apparatus that includes an offsetinterposer according to any of the several disclosed embodiments as setforth herein in the various embodiments and their art-recognizedequivalents. The elements, materials, geometries, dimensions, andsequence of operations can all be varied to suit particular I/O couplingrequirements including offset interposer embodiments and theirequivalents.

Although a die may refer to a processor chip, an RF chip, an RFIC chip,IPD chip, or a memory chip may be mentioned in the same sentence, but itshould not be construed that they are equivalent structures. Referencethroughout this disclosure to “one embodiment” or “an embodiment” meansthat a particular feature, structure, or characteristic described inconnection with the embodiment is included in at least one embodiment ofthe present invention. The appearance of the phrases “in one embodiment”or “in an embodiment” in various places throughout this disclosure arenot necessarily all referring to the same embodiment. Furthermore, theparticular features, structures, or characteristics may be combined inany suitable manner in one or more embodiments.

Terms such as “upper” and “lower” “above” and “below” may be understoodby reference to the illustrated X-Z coordinates, and terms such as“adjacent” may be understood by reference to X-Y coordinates or to non-Zcoordinates.

The Abstract is provided to comply with 37 C.F.R. § 1.72(b) requiring anabstract that will allow the reader to quickly ascertain the nature andgist of the technical disclosure. It is submitted with the understandingthat it will not be used to interpret or limit the scope or meaning ofthe claims.

In the foregoing Detailed Description, various features are groupedtogether in a single embodiment for the purpose of streamlining thedisclosure. This method of disclosure is not to be interpreted asreflecting an intention that the claimed embodiments of the inventionrequire more features than are expressly recited in each claim. Rather,as the following claims reflect, inventive subject matter lies in lessthan all features of a single disclosed embodiment. Thus the followingclaims are hereby incorporated into the Detailed Description, with eachclaim standing on its own as a separate preferred embodiment.

It will be readily understood to those skilled in the art that variousother changes in the details, material, and arrangements of the partsand method stages which have been described and illustrated in order toexplain the nature of this invention may be made without departing fromthe principles and scope of the invention as expressed in the subjoinedclaims.

What is claimed is:
 1. A package-on-package (POP) structure comprising:a processor device mechanically and electrically coupled to a substrate;a first ball grid array (BGA) electrically and mechanically coupled tothe processor; an interposer electrically and mechanically coupled tothe processor device, wherein the interposer comprises: a first sidecomprising a first array of pads, wherein a first pad and a second padof the first array are adjacent to each other on the first side, andwherein the first pad is coupled to a first electrical interconnectstructure of the first BGA, and wherein the second land side pad iscoupled to a second electrical interconnect structure of the first BGA,and wherein the first array of pads comprises a first perimeterdimension; and a second side comprising a second array of pads, whereina first pad and a second pad of the second array are adjacent to eachother on the second side, and wherein the first pad on the second sideis electrically coupled with the first pad on the first side through theinterposer, and wherein the second pad on the second side and the secondpad on the first side are electrically coupled to each other through theinterposer, and wherein the second array of pads comprises a secondperimeter dimension, wherein the first perimeter dimension is largerthan the second perimeter dimension; a second BGA comprising a pluralityof electrical interconnect structures, wherein the first pad of thesecond array of pads is coupled with a first electrical interconnectstructure of the second BGA, and wherein the second pad of the secondarray of pads is coupled with a second electrical interconnect structureof the second BGA; and a memory device mechanically and electricallycoupled to the second BGA.